Altera cyclone V Technical Reference page 1049

cv_5v4
2016.10.28
Bit
26
disable_boot
25
expect_boot_ack
24
enable_boot
23
ccs_expected
SD/MMC Controller
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Name
When software sets this bit along with start_cmd,
CIU terminates the boot operation. Do NOT set
disable_boot and enable_boot together.
Value
0x0
0x1
When Software sets this bit along with enable_boot,
CIU expects a boot acknowledge start pattern of 0-1-
0 from the selected card.
Value
0x0
0x1
This bit should be set only for mandatory boot mode.
When Software sets this bit along with start_cmd,
CIU starts the boot sequence for the corresponding
card by asserting the CMD line low. Do NOT set
disable_boot and enable_boot together
Value
0x0
0x1
If the command expects Command Completion
Signal (CCS) from the CE-ATA device, the software
should set this control bit. SD/MMC sets Data
Transfer Over (DTO) bit in RINTSTS register and
generates interrupt to host if Data Transfer Over
interrupt is not masked.
Value
0x0
0x1
Description
Description
Boot not Terminated
Terminate Boot
Description
No Boot ACK
Expect Boot ACK
Description
Disable Boot
Enable Boot
Description
Interrupts are not enabled in CE-ATA device
(nIEN = 1 in ATA control register), or
command does not expect CCS from device
Interrupts are enabled in CE-ATA device
(nIEN = 0), and RW_BLK command expects
command completion signal from CE-ATA
device
14-103
cmd
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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