Altera cyclone V Technical Reference page 1062

14-116
rintsts
Bit
9
bds
8
bar
7
dcrc
6
rcrc
5
rxdr
Altera Corporation
Name
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Description
Description
Data read timeout (DRTO)/Boot Data Start
(BDS)
Clears Data read timeout (DRTO)/Boot Data
Start (BDS)
Description
Response timeout (RTO)/Boot Ack Received
(BAR)
Clears Response timeout (RTO)/Boot Ack
Received (BAR)
Description
Data CRC error (DCRC)
Clears Data CRC error (DCRC)
Description
Response CRC error (RCRC)
Clears Response CRC error (RCRC)
Description
Receive FIFO data request (RXDR)
Clears Receive FIFO data request (RXDR)
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
SD/MMC Controller
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