Altera cyclone V Technical Reference page 1136

cv_5v4
2016.10.28
31 30
15 14
indrd Fields
Bit
7:6
num_ind_ops_done
5
ind_ops_done_status
4
rd_queued
3
sram_full
Quad SPI Flash Controller
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29 28 27 26
13 12 11 10
Reserved
Name
This field contains the number of indirect operations
which have been completed. This is used in conjunc‐
tion with the indirect completion status field (bit 5).
This field is set to 1 when an indirect operation has
completed. Write a 1 to this field to clear it.
Value
0x1
0x0
Two indirect read operations have been queued
Value
0x1
0x0
SRAM full and unable to immediately complete an
indirect operation. Write a 1 to this field to clear it. ;
indirect operation (status)
Value
0x1
0x0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
num_ind_
ops_done
RO 0x0
Description
Description
Indirect Op Complete operation
Indirect Op Not Complete
Description
Queued Indirect Read
No Queued Read
Description
Sram Full- Cant complete operation
SRram Not Full
21 20 19 18
5 4 3 2
ind_ rd_ sram_ rd_
ops_ queue full statu
done_ d s
RW
statu
RO 0x0 RO
s
0x0 0x0
RW
0x0
Access
15-47
indrd
17 16
1 0
cance start
l
RW 0x0
RW
0x0
Reset
RO 0x0
RW 0x0
RO 0x0
RW 0x0
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