Altera cyclone V Technical Reference page 1072

Hard processor system
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14-126
usrid
31
30
15
14
debnce Fields
Bit
23:0
debounce_count
usrid
Module Instance
sdmmc
Offset:
0x68
Access:
RW
31
30
15
14
usrid Fields
Bit
31:0
usr_id
verid
Altera Corporation
29
28
27
26
Reserved
13
12
11
10
Name
Number of host clocks l4_mp_clk used by debounce
filter logic; typical debounce time is 5-25 ms.
29
28
27
26
13
12
11
10
Name
User identification field; Value is 0x7967797.
Bit Fields
25
24
23
22
9
8
7
6
debounce_count
RW 0xFFFFFF
Description
Base Address
0xFF704000
Bit Fields
25
24
23
22
usr_id
RW 0x7967797
9
8
7
6
usr_id
RW 0x7967797
Description
21
20
19
18
debounce_count
RW 0xFFFFFF
5
4
3
2
Access
Register Address
0xFF704068
21
20
19
18
5
4
3
2
Access
cv_5v4
2016.10.28
17
16
1
0
Reset
RW
0xFFFFF
F
17
16
1
0
Reset
RW
0x79677
97
SD/MMC Controller
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