Altera cyclone V Technical Reference page 1079

cv_5v4
2016.10.28
Bit
1
fb
0
swr
pldmnd
See Field Description.
Module Instance
sdmmc
Offset:
0x84
Access:
WO
31 30
15 14
SD/MMC Controller
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Name
Controls whether the AHB Master interface performs
fixed burst transfers or not. Will use only SINGLE,
INCR4, INCR8 or INCR16 during start of normal
burst transfers.
Value
0x1
0x0
This bit resets all internal registers of the DMA
Controller. It is automatically cleared after 1 clock
cycle.
Value
0x1
0x0
0xFF704000
29 28 27 26
13 12 11 10
Description
Description
AHB Master Fixed Burst
Non Fixed Burst - default
Description
Resets DMA Internal Registers
No reset - default
Base Address
Bit Fields
25 24 23 22
pd
WO 0x0
9 8 7 6
pd
WO 0x0
pldmnd
Access
Register Address
0xFF704084
21 20 19 18
5 4 3 2
14-133
Reset
RW 0x0
RW 0x0
17 16
1 0
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