Altera cyclone V Technical Reference page 1114

Hard processor system

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Quad SPI Flash Controller

Send Feedback

This bit controls the write protect pin of the flash

devices. The signal qspi_mo2_wpn needs to be

resynchronized to the generated memory clock as

Peripheral chip select line output decode type. As per

perseldec, if perseldec = 0, the decode is select 1 of 4

decoding on signals, qspi_n_ss_out[3:0], The asserted

decode line goes to 0. If perseldec = 1, the signals

qspi_n_ss_out[3:0] require an external 4 to 16

Select between '1 of 4 selects' or 'external 4-to-16

decode'. The qspi_n_ss_out[3:0] output signals are

This bit can select the Direct Access Controller/

Indirect Access Controller or legacy mode.If legacy

mode is selected, any write to the controller via the

AHB interface is serialized and sent to the FLASH

device. Any valid AHB read will pop the internal RX-

FIFO, retrieving data that was forwarded by the

external FLASH device on the SPI lines, byte transfers

of 4, 2 or 1 are permitted and controlled via the

HSIZE input.

Enable Write Protect

Disable Write Protect

Select external 4-to-16 decode

Selects 1 of 4 qspi_n_ss_out[3:0]

Use Direct/Indirect Access Controller

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