Altera cyclone V Technical Reference page 1064

14-118
status
Module Instance
sdmmc
Offset:
0x48
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
response_index
RO 0x0
status Fields
Bit
29:17
fifo_count
16:11
response_index
10
data_state_mc_busy
9
data_busy
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
data_
state
_mc_
busy
RO
0x0
Name
FIFO count - Number of filled locations in FIFO
Index of previous response, including any auto-stop
sent by core
Data transmit or receive state-machine is busy.
Value
0x1
0x0
Inverted version of raw selected card_​data[0]. The
default can be cardpresent or not present depend on
cdata_in.
Value
0x1
0x0
Base Address
0xFF704000
Bit Fields
25 24 23 22
fifo_count
RO 0x0
9 8 7 6
data_ data_ command_fsm_states
busy 3_
RO 0x0
statu
RO
s
0x0
RO
0x1
Description
Description
Data State MC busy
Data State MC not busy
Description
card data busy
card data not busy
Register Address
0xFF704048
21 20 19 18
5 4 3 2
fifo_ fifo_
full empty
RO RO
0x0 0x1
Access
cv_5v4
2016.10.28
17 16
response
_index
RO 0x0
1 0
fifo_ fifo_rx_
tx_ watermar
water k
mark
RO 0x0
RO
0x1
Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
SD/MMC Controller
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