Altera cyclone V Technical Reference page 1127

15-38
rxthresh
txthresh Fields
Bit
3:0
level
rxthresh
Device Instruction Register
Module Instance
qspiregs
Offset:
0x34
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
rxthresh Fields
Bit
3:0
level
irqstat
The status fields in this register are set when the described event occurs and the interrupt is enabled in the
mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each
cleared by writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when legacy SPI mode is
active.
Module Instance
qspiregs
Altera Corporation
Name
Defines the level at which the transmit FIFO not full
interrupt is generated
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Defines the level at which the receive FIFO not empty
interrupt is generated
Description
Base Address
0xFF705000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF705000
Access
Register Address
0xFF705034
21 20 19 18
5 4 3 2
Access
Register Address
0xFF705040
Quad SPI Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x1
17 16
1 0
level
RW 0x1
Reset
RW 0x1
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