Altera cyclone V Technical Reference page 1050

14-104
cmd
Bit
22
read_ceata_device
21
update_clock_
registers_only
20:16
card_number
Altera Corporation
Name
Software should set this bit to indicate that CE-ATA
device is being accessed for read transfer. This bit is
used to disable read data timeout indication while
performing CE-ATA read transfers. Maximum value
of I/O transmission delay can be no less than 10
seconds. SD/MMC should not indicate read data
timeout while waiting for data from CE-ATA device.
Value
0x0
0x1
Following register values transferred into card clock
domain: CLKDIV, CLRSRC, CLKENA. Changes card
clocks (change frequency, truncate off or on, and set
low-frequency mode); provided in order to change
clock frequency or stop clock without having to send
command to cards. During normal command
sequence, when update_clock_registers_only = 0,
following control registers are transferred from BIU
to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ,
BYTCNT. CIU uses new register values for new
command sequence to card(s). When bit is set, there
are no Command Done interrupts because no
command is sent to SD_MMC_CEATA cards.
Value
0x0
0x1
Card number in use must always be 0.
Description
Description
Host is not performing read access (RW_REG
or RW_BLK) towards CE-ATA device
Host is performing read access (RW_REG or
RW_BLK) towards CE-ATA device
Description
Normal command sequence
Do not send commands, just update clock
register value into card clock domain
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
SD/MMC Controller
Send Feedback