Altera cyclone V Technical Reference page 1085

cv_5v4
2016.10.28
Bit
2
fbe
1
ri
0
ti
dscaddr
See Field Description.
Module Instance
sdmmc
Offset:
0x94
Access:
RO
31 30
15 14
SD/MMC Controller
Send Feedback
Name
When set with Abnormal Interrupt Summary Enable,
the Fatal Bus Error Interrupt is enabled.
Value
0x1
0x0
Enables and Disables Receive Interrupt when Normal
Interrupt Summary Enable is set.
Value
0x1
0x0
Enables and Disables Transmit Interrupt when
Normal Interrupt Summary Enable is set.
Value
0x1
0x0
0xFF704000
29 28 27 26
13 12 11 10
Description
Description
Fatal Bus Error Interrupt is enabled
Fatal Bus Error Interrupt is disabled
Description
Receive Interrupt is enabled
Receive Interrupt is disabled
Description
Transmit Interrupt is enabled
Transmit Interrupt is disabled
Base Address
Bit Fields
25 24 23 22
hda
RO 0x0
9 8 7 6
hda
RO 0x0
dscaddr
Access
Register Address
0xFF704094
21 20 19 18
5 4 3 2
14-139
Reset
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
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