Altera cyclone V Technical Reference page 1028

14-82
Alternative Boot Operation for eMMC Card Devices
In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO
buffer to the system memory as soon as the level specified in the
register is reached.
d. The software driver must terminate the boot process by instructing the controller to send the SD/
SDIO GO_IDLE_STATE command:
• Reset the
• Set the
e. At the end of a successful boot data transfer from the card, the following interrupts are generated:
• The
• The
f. If an error occurs in the boot ACK pattern (0b010) or an EBE occurs:
• The controller does not generate a Boot ACK Received interrupt.
• The controller detects Boot Data Start and generates a Boot Data Start interrupt.
• The controller continues to receive boot data.
• The application must abort the boot process after receiving a Boot Data Start interrupt.
g. In internal DMA controller mode:
• If the software driver creates more descriptors than required by the received boot data, the extra
descriptors are not closed by the controller.
• If the software driver creates fewer descriptors than required by the received boot data, the
controller generates a Descriptor Unavailable interrupt and does not transfer any further data to
system memory.
h. If N
there is an error associated with the start or end bit, the SBE or EBE interrupt is also generated.
The alternative boot operation for eMMC card devices is complete. Do not execute the remaining steps
and 16).
(15
15.Wait for the Command Done interrupt.
16.This step handles the case where a start-acknowledge pattern is not expected (
set to 0 in
a. If the Boot Data Start interrupt is not received from the controller within 1 second of initiating the
command
discovery.
• The DMA descriptor is closed.
• The
• The
b. If a Boot Data Start interrupt is received, the boot data is being received from the card device. When
the DMA engine is not in internal DMA controller mode, the software driver can then initiate a
data read from the controller based on the
In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO
buffer to the system memory as soon as the level specified in the
register is reached.
c. The software driver must terminate the boot process by instructing the controller to send the SD/
SDIO GO_IDLE_STATE (CMD0) command:
• Reset the
• Set the
d. At the end of a successful boot data transfer from the card, the following interrupts are generated:
Altera Corporation
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register to 0.
cmdarg
bit of the
start_cmd
bit and bit in the
cmd dto
bit in the register, in internal DMA controller mode only
ri idsts
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is violated between data block transfers, a DRTO interrupt is asserted. Apart from this, if
AC
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step 11).
(step 11), the software driver must discontinue the boot process and start with normal
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In internal DMA controller mode:
bit in the register is set to 1, indicating Boot Data Start timeout.
ces idsts
bit of the register is not set.
ri idsts
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register to 0.
cmdarg
bit in the
start_cmd
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register to 1, and all other bits to 0.
cmd
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register
rintsts
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interrupt bit in the
rxdr
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register to 1, and all other bits to 0.
cmd
field of the
rx_wmark fifoth
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expect_boot_ack
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register.
rintsts
field of the
rx_wmark fifoth
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SD/MMC Controller
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cv_5v4
2016.10.28
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