Altera cyclone V Technical Reference page 1031
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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cv_5v4
2016.10.28
Register
resp1
on page 14-108
resp2
on page 14-109
resp3
on page 14-109
mintsts
on page 14-
110
rintsts
on page 14-
114
status
on page 14-117
fifoth
on page 14-120
cdetect
on page 14-
122
wrtprt
on page 14-123
tcbcnt
on page 14-124
tbbcnt
on page 14-125
debnce
on page 14-125
usrid
on page 14-126
verid
on page 14-126
hcon
on page 14-127
uhs_reg
on page 14-
129
rst_n
on page 14-130
bmod
on page 14-131
pldmnd
on page 14-133
dbaddr
on page 14-134
idsts
on page 14-134
idinten
on page 14-
137
dscaddr
on page 14-
139
bufaddr
on page 14-
140
cardthrctl
on page
14-140
SD/MMC Controller
Send Feedback
Offset
Width Acces
s
0x34
32
RO
0x38
32
RO
0x3C
32
RO
0x40
32
RO
0x44
32
RW
0x48
32
RO
0x4C
32
RW
0x50
32
RO
0x54
32
RO
0x5C
32
RO
0x60
32
RO
0x64
32
RW
0x68
32
RW
0x6C
32
RO
0x70
32
RO
0x74
32
RW
0x78
32
RW
0x80
32
RW
0x84
32
WO
0x88
32
RW
0x8C
32
RW
0x90
32
RW
0x94
32
RO
0x98
32
RO
0x100
32
RW
SDMMC Module Address Map
Reset Value
Response Register 1
0x0
Response Register 2
0x0
Response Register 3
0x0
Masked Interrupt Status Register
0x0
Raw Interrupt Status Register
0x0
Status Register
0x106
FIFO Threshold Watermark
0x3FF0000
Register
Card Detect Register
0x1
Write Protect Register
0x1
Transferred CIU Card Byte Count
0x0
Register
Transferred Host to BIU-FIFO
0x0
Byte Count Register
Debounce Count Register
0xFFFFFF
User ID Register
0x7967797
Version ID Register
0x5342240A
Hardware Configuration Register
0xC43081
UHS-1 Register
0x0
Hardware Reset Register
0x1
Bus Mode Register
0x0
Poll Demand Register
0x0
Descriptor List Base Address
0x0
Register
Internal DMAC Status Register
0x0
Internal DMAC Interrupt Enable
0x0
Register
Current Host Descriptor Address
0x0
Register
Current Buffer Descriptor Address
0x0
Register
Card Threshold Control Register
0x0
14-85
Description
Altera Corporation
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