Altera cyclone V Technical Reference page 1033

cv_5v4
2016.10.28
ctrl Fields
Bit
25
use_internal_dmac
11
ceata_device_
interrupt_status
10
send_auto_stop_ccsd
SD/MMC Controller
Send Feedback
Name
Enable and Disable Internal DMA transfers.
Value
0x0
0x1
Software should appropriately write to this bit after
power-on reset or any other reset to CE-ATA device.
After reset, usually CE-ATA device interrupt is
disabled (nIEN = 1). If the host enables CE-ATA
device interrupt, then software should set this bit.
Value
0x0
0x1
Always set send_auto_stop_ccsd and send_ccsd bits
together; send_auto_stop_ccsd should not be set
independent of send_ccsd. When set, SD/MMC
automatically sends internally generated STOP
command (CMD12) to CE-ATA device. After sending
internally-generated STOP command, Auto
Command Done (ACD) bit in RINTSTS is set and
generates interrupt to host if Auto CommandDone
interrupt is not masked. After sending the CCSD, SD/
MMC automatically clears send_auto_stop_ccsd bit.
Value
0x0
0x1
Description
Description
The host performs data transfers thru slave
interface
Internal DMAC used for data transfer
Description
Interrupts not enabled in CE-ATA device
Interrupts are enabled in CE-ATA device
Description
Clear bit if SD/MMC does not reset the bit
Send internally generated STOP.
14-87
ctrl
Access Reset
RW 0x0
RW 0x0
RW 0x0
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