Altera cyclone V Technical Reference page 1080

14-134
dbaddr
pldmnd Fields
Bit
31:0
pd
dbaddr
See Field Descriptor
Module Instance
sdmmc
Offset:
0x88
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dbaddr Fields
Bit
31:2
sdl
idsts
Sets Internal DMAC Status Fields
Module Instance
sdmmc
Altera Corporation
Name
If the OWN bit of a descriptor is not set, the FSM
goes to the Suspend state. The host needs to write any
value into this register for the IDMAC FSM to resume
normal descriptor fetch operation.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Contains the base address of the First Descriptor. This
is the byte address divided by 4.
Description
Base Address
0xFF704000
Bit Fields
25 24 23 22
sdl
RW 0x0
9 8 7 6
sdl
RW 0x0
Description
Base Address
0xFF704000
Access
Register Address
0xFF704088
21 20 19 18
5 4 3 2
Access
Register Address
0xFF70408C
cv_5v4
2016.10.28
Reset
WO 0x0
17 16
1 0
Reserved
Reset
RW 0x0
SD/MMC Controller
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