Altera cyclone V Technical Reference page 1143

15-54
flashcmd
flashcmd
Module Instance
qspiregs
Offset:
0x90
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
enwrdata numwrdatabytes
RW 0x0 RW 0x0
flashcmd Fields
Bit
31:24
cmdopcode
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
cmdopcode
RW 0x0
13 12 11 10
numdummybytes
Name
The command opcode field should be setup before
triggering the command. For example, 0x20 maps to
SubSector Erase. Writeing to the execute field (bit 0)
of this register launches the command. NOTE : Using
this approach to issue commands to the device will
make use of the instruction type of the device instruc‐
tion configuration register. If this field is set to 2'b00,
then the command opcode, command address,
command dummy bytes and command data will all
be transferred in a serial fashion. If this field is set to
2'b01, then the command opcode, command address,
command dummy bytes and command data will all
be transferred in parallel using DQ0 and DQ1 pins. If
this field is set to 2'b10, then the command opcode,
command address, command dummy bytes and
command data will all be transferred in parallel using
DQ0, DQ1, DQ2 and DQ3 pins.
Base Address
0xFF705000
Bit Fields
25 24 23 22
enrdd numrddatabytes
ata
RW
0x0
9 8 7 6
RW 0x0
Description
Register Address
0xFF705090
21 20 19 18
encmd enmod
addr ebit
RW 0x0
RW RW
0x0 0x0
5 4 3 2
Reserved
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
numaddrbytes
RW 0x0
1 0
cmdex execcmd
ecsta
RW 0x0
t
RO
0x0
Access Reset
RW 0x0
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