Altera cyclone V Technical Reference page 1032

14-86
ctrl
Register
back_end_power_r
page 14-141
data on page 14-142
ctrl
Sets various operating condiitions.
Module Instance
sdmmc
Offset:
0x0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
Altera Corporation
Offset
on 0x104
0x200
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
ceata send_
_ auto_
devic stop_
e_ ccsd
inter
RW
rupt_
0x0
statu
s
RW
0x0
Width Acces Reset Value
s
32 RW 0x0
32 RW 0x0
Base Address
0xFF704000
Bit Fields
25 24 23 22
use_
inter
nal_
dmac
RW
0x0
9 8 7 6
send_ abort send_ read_
ccsd _ irq_ wait
read_ respo
RW RW
data nse
0x0 0x0
RW RW
0x0 0x0
Description
Back End Power Register
Data FIFO Access
Register Address
0xFF704000
21 20 19 18
Reserved
5 4 3 2
Reser int_ Reser dma_
ved enabl ved reset
e
RW
RW 0x0
0x0
cv_5v4
2016.10.28
17 16
1 0
fifo_ controll
reset er_reset
RW RW 0x0
0x0
SD/MMC Controller
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