Altera cyclone V Technical Reference page 1134

cv_5v4
2016.10.28
uppwrprot Fields
Bit
31:0
subsector
wrprot
Module Instance
qspiregs
Offset:
0x58
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Quad SPI Flash Controller
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Name
The block number that defines the upper block in the
range of blocks that is to be locked from writing. The
definition of a block in terms of number of bytes is
programmable via the Device Size Configuration
register.
0xFF705000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
wrprot
Access
Register Address
0xFF705058
21 20 19 18
5 4 3 2
15-45
Reset
RW 0x0
17 16
1 0
en inv
RW RW 0x0
0x0
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