Data Width Sizing - Altera Cyclone V Device Handbook

5-14
Lightweight HPS-to-FPGA Bridge
Lightweight HPS-to-FPGA Bridge
The master interface into the FPGA fabric operates in the h2f_lw_axi_clk clock domain provided by
custom logic in the FPGA fabric. The slave interface of the bridge in the HPS logic operates in the l4_mp_clk
clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any
clock domain, asynchronous from the HPS.
The lightweight HPS-to-FPGA bridge has one reset signal, lwhps2fpga_bridge_rst_n. The reset
manager drives this signal to the lightweight HPS-to-FPGA bridge on a cold or warm reset.
Related Information
• Clock Manager
For information about the l3_main_clk and l4_mp_clk clocks, refer to the Clock Manager chapter.
• Reset Manager
For more information about the reset manager, refer to the Reset Manager chapter.
• HPS Component Interfaces
For information about the f2h_axi_clk clock, refer to the HPS Component Interfaces chapter.
GPV Clocks
The FPGA-to-HPS and HPS-to-FPGA bridges have GPV slave interfaces, mastered by the lightweight
HPS-to-FPGA bridge. These interfaces operate in the l4_mp_clk clock domain. Even if you do not use
the lightweight HPS-to-FPGA bridge in your FPGA design, you must ensure that a valid l4_mp_clk clock
is being generated, so that the GPV registers in the HPS-to-FPGA and FPGA-to-HPS bridges can be
programmed. The GPV logic in all three bridges is in the l4_mp_clk domain.
Related Information
The Global Programmers View

Data Width Sizing

-The HPS-to-FPGA and FPGA-to-HPS bridges allow 32-, 64-, and 128-bit interfaces to be exposed to the
FPGA fabric. For 32-bit and 128-bit interfaces, the bridge performs data width conversion to the fixed 64-bit
interface within the HPS. This conversion is called upsizing in the case of data being converted from a 64-bit
interface to a 128-bit interface. It is called downsizing in the case of data being converted from a 64-bit
interface to a 32-bit interface. If an exclusive access is split into multiple transactions, the transactions lose
their exclusive access information.
During the upsizing or downsizing process, transactions can also be resized using a data merging technique.
For example, in the case of a 32-bit to 64-bit upsizing, if the size of each beat entering the bridge's 32-bit
interface is only two bytes, the bridge can merge up to four beats to form a single 64-bit beat. Similarly, in
the case of a 128-bit to 64-bit downsizing, if the size of each beat entering the bridge's 128-bit interface is
only four bytes, the bridge can merge two beats to form a single 64-bit beat.
The bridges do not perform transaction merging for accesses marked as noncacheable.
Note: You can set the bypass_merge bit in the GPV to prevent the bridge from merging data and
responses. If the bridge merges multiple responses into a single response, that response is the one
with the highest priority. The response types have the following priorities:
Altera Corporation
on page 2-1
on page 3-1
on page 28-1
on page 5-3
cv_54005
2013.12.30
HPS-FPGA AXI Bridges
Send Feedback