Altera cyclone V Technical Reference page 1046

Hard processor system
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14-100
cmdarg
Bit
2
cmd
1
re
0
cd
cmdarg
See Field Description.
Module Instance
sdmmc
Offset:
0x28
Access:
RW
31
30
15
14
Altera Corporation
Name
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
29
28
27
26
13
12
11
10
Description
Description
Command Done Mask
Command Done No Mask
Description
Response error Mask
Response error No Mask
Description
Card Detected Mask
Card Detect No Mask
Base Address
0xFF704000
Bit Fields
25
24
23
22
cmd_arg
RW 0x0
9
8
7
6
cmd_arg
RW 0x0
Access
Register Address
0xFF704028
21
20
19
18
5
4
3
2
cv_5v4
2016.10.28
Reset
RW
0x0
RW
0x0
RW
0x0
17
16
1
0
SD/MMC Controller
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