Altera cyclone V Technical Reference page 1005

cv_5v4
2016.10.28
Internal DMA Controller Transmission Sequences
To use the internal DMA controller to transmit data, perform the following steps:
1. The host sets up the Descriptor fields (DES0—DES3) for transmission and sets the OWN bit
(DES0[31]) to 1. The host also loads the data buffer in system memory with the data to be written to
the SD card.
2. The host writes the appropriate write data command (SD/SDIO WRITE_BLOCK or
WRITE_MULTIPLE_BLOCK) to the
data transfer needs to be performed.
3. The host sets the required transmit threshold level in the
4. The internal DMA controller engine fetches the descriptor and checks the OWN bit. If the OWN bit is
set to 0, the host owns the descriptor. In this case, the internal DMA controller enters the suspend state
and asserts the Descriptor Unable interrupt. The host then needs to set the descriptor OWN bit to 1
and release the DMA controller by writing any value to the
5. The host must write the descriptor base address to the
6. The internal DMA controller waits for the Command Done (
1, with no errors from the BIU. This condition indicates that a transfer can be done.
7. The internal DMA controller engine waits for a DMA interface request from BIU. The BIU divides each
transfer into smaller chunks. Each chunk is an internal request to the DMA. This request is generated
based on the transmit threshold value.
8. The internal DMA controller fetches the transmit data from the data buffer in the system memory and
transfers the data to the FIFO buffer in preparation for transmission to the card.
9. When data spans across multiple descriptors, the internal DMA controller fetches the next descriptor
and continues with its operation with the next descriptor. The Last Descriptor bit in the descriptor
DES0 field indicates whether the data spans multiple descriptors or not.
10.When data transmission is complete, status information is updated in the
bit to 1, if enabled. Also, the OWN bit is set to 0 by the DMA controller by updating the DES0 field
ti
of the descriptor.
Internal DMA Controller Reception Sequences
To use the internal DMA controller to receive data, perform the following steps:
1. The host sets up the descriptor fields (DES0—DES3) for reception and sets the OWN (DES0 [31]) to 1.
2. The host writes the read data command to the
determines that a read data transfer needs to be performed.
3. The host sets the required receive threshold level in the
4. The internal DMA controller engine fetches the descriptor and checks the OWN bit. If the OWN bit is
set to 0, the host owns the descriptor. In this case, the internal DMA controller enters suspend state and
asserts the Descriptor Unable interrupt. The host then must set the descriptor OWN bit to 1 and release
the DMA controller by writing any value to the
5. The host must write the descriptor base address to the
6. The internal DMA controller waits for the
from the BIU. This condition indicates that a transfer can be done.
7. The internal DMA controller engine waits for a DMA interface request from the BIU. The BIU divides
each transfer into smaller chunks. Each chunk is an internal request to the DMA. This request is
generated based on the receive threshold value.
SD/MMC Controller
Send Feedback
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Internal DMA Controller Transmission Sequences
register. The internal DMA controller determines that a write
cmd
tx_wmark
pldmnd
register.
dbaddr
CD
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register in BIU. The internal DMA controller
cmd
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rx_wmark
register.
pldmnd
register.
dbaddr
bit in the
CD rintsts
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field in the register.
fifoth
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register.
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) bit in the register to be set to
rintsts
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register by setting the
idsts
field in the register.
fifoth
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register to be set to 1, with no errors
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Altera Corporation
14-59
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