Altera cyclone V Technical Reference page 1076

14-130
rst_n
Module Instance
sdmmc
Offset:
0x74
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
uhs_reg Fields
Bit
16
ddr_reg
0
volt_reg
rst_n
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Determines the voltage fed to the buffers by an
external voltage regulator.
0x0
0x1
Determines the voltage fed to the buffers by an
external voltage regulator. These bits function as the
output of the host controller and are fed to an external
voltage regulator. The voltage regulator must switch
the voltage of the buffers of a particular card to either
3.3V or 1.8V, depending on the value programmed in
the register.
Value
0x0
0x1
Base Address
0xFF704000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Value Description
Non-DDR mode
DDR mode
Description
Buffers supplied with 3.3V Vdd
Buffers supplied with 1.8V Vdd
Register Address
0xFF704074
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
17 16
ddr_reg
RW 0x0
1 0
volt_reg
RW 0x0
Reset
RW 0x0
RW 0x0
SD/MMC Controller
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