Altera cyclone V Technical Reference page 1095

15-6
Indirect Write Operation
Alternatively, you can configure the fill level watermark of the SRAM in the
the SRAM fill level passes the watermark level, the indirect transfer watermark interrupt is generated. You
can disable this watermark feature by writing a value of all zeroes to the
For the final bytes of data read by the quad SPI controller and placed in the SRAM, if the watermark level
is greater than zero, the indirect transfer watermark interrupt is generated even when the actual SRAM fill
level has not risen above the watermark.
If the address of the read access is outside the range of the indirect trigger address, one of the following
actions occurs:
• When direct access mode is enabled, the read uses direct access mode.
• When direct access mode is disabled, the slave returns an error back to the requesting master.
You can cancel an indirect operation by setting the cancel indirect read bit (
to 1. For more information, refer to the "Indirect Read Operation with DMA Disabled" section.
Related Information
Indirect Read Operation with DMA Disabled
Indirect Write Operation
An indirect write operation programs data from the SRAM to the flash memory. The indirect write
operations are controlled by the following registers:
• Indirect write transfer register (
• Indirect write transfer watermark register (
• Indirect write transfer start address register (
• Indirect write transfer number bytes register (
•
indaddrtrig
These registers need to be configured prior to issuing indirect write operations. The start address needs to
be defined in the
indwrcnt
operation from the SRAM to the flash memory.
To write data from the SRAM to the flash device, an external master issues 32-bit write transactions to the
data slave. The address of the write access must be in the indirect address range. You can configure the
indirect address through the
last word of an indirect transfer. On the final write, the external master may issue a 32-bit, 16-bit or 8-bit
write to complete the transfer. If there are less than four bytes of data to write on the last transfer, the
external master can still issue a 32-bit write and the quad SPI controller discards the extra bytes.
The SRAM size can limit the amount of data that the quad SPI controller can accept from the external
master. If the SRAM is not full at the point of the write access, the data is pushed to the SRAM with
minimum latency. If the external master attempts to push more data to the SRAM than the SRAM can
accept, the quad SPI controller backpressures the external master with wait states. When the SRAM
resource is freed up by pushing the data from SRAM to the flash memory, the SRAM is ready to receive
more data from the external master. When the SRAM holds an equal or greater number of bytes than the
size of a flash page, or when the SRAM holds all the remaining bytes of the current indirect transfer, the
quad SPI controller initiates a write operation to the flash memory.
The processor can also use the SRAM fill level, in the
data into the SRAM.
Alternatively, you can configure the fill level watermark of the SRAM in the
the SRAM fill level falls below the watermark level, an indirect transfer watermark interrupt is generated
to tell the software to write the next page of data to the SRAM. Because the quad SPI controller initiates
Altera Corporation
register
register and the total number of bytes to be written is specified in the
indwrstaddr
register. The start indirect write bit (
indaddrtrig
on page 15-15
)
indwr
)
indwrwater
indwrstaddr
)
indwrcnt
) of the
start
register. The external master can issue 32-bit writes until the
sramfill
indrdwater
indrdwater
) of the
cancel
)
register triggers the indirect write
indwr
register, to control when to write more
indwrwater
Quad SPI Flash Controller
cv_5v4
2016.10.28
register. When
register.
register
indrd
register. When
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