Altera cyclone V Technical Reference page 1071

cv_5v4
2016.10.28
tbbcnt
Tracks number of bytes transferred between Host and FIFO.
Module Instance
sdmmc
Offset:
0x60
Access:
RO
31 30
15 14
tbbcnt Fields
Bit
31:0
trans_fifo_byte_count
debnce
Module Instance
sdmmc
Offset:
0x64
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
SD/MMC Controller
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0xFF704000
29 28 27 26
13 12 11 10
Name
Number of bytes transferred between Host/DMA
memory and BIU FIFO. In 32-bit AMBA data-bus-
width modes, register should be accessed in full to
avoid read-coherency problems. Both TCBCNT and
TBBCNT share same coherency register.
0xFF704000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
trans_fifo_byte_count
RO 0x0
9 8 7 6
trans_fifo_byte_count
RO 0x0
Description
Base Address
tbbcnt
Register Address
0xFF704060
21 20 19 18
5 4 3 2
Access
Register Address
0xFF704064
14-125
17 16
1 0
Reset
RO 0x0
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