Altera cyclone V Technical Reference page 1120

cv_5v4
2016.10.28
Module Instance
qspiregs
Offset:
0xC
Access:
RW
31 30
15 14
delay Fields
Bit
31:24
nss
23:16
btwn
15:8
after
7:0
init
rddatacap
Module Instance
qspiregs
Quad SPI Flash Controller
Send Feedback
0xFF705000
29 28 27 26
nss
RW 0x0
13 12 11 10
after
RW 0x0
Name
Delay in master reference clocks for the length that
the master mode chip select outputs are de-asserted
between transactions. The minimum delay is always
qspi_sck_out period to ensure the chip select is never
re-asserted within an qspi_sck_out period.
Delay in master reference clocks between one chip
select being de-activated and the activation of
another. This is used to ensure a quiet period between
the selection of two different slaves and requires the
transmit FIFO to be empty.
Delay in master reference clocks between last bit of
current transaction and deasserting the device chip
select (qspi_n_ss_out). By default, the chip select will
be deasserted on the cycle following the completion of
the current transaction.
Delay in master reference clocks between setting
qspi_n_ss_out low and first bit transfer.
0xFF705000
Base Address
Bit Fields
25 24 23 22
9 8 7 6
Description
Base Address
rddatacap
Register Address
0xFF70500C
21 20 19 18
btwn
RW 0x0
5 4 3 2
init
RW 0x0
Access
Register Address
0xFF705010
15-31
17 16
1 0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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