Altera cyclone V Technical Reference page 1067

cv_5v4
2016.10.28
31 30
Reserved dw_dma_multiple_
transaction_size
RW 0x0
15 14
Reserved
fifoth Fields
Bit
30:28
dw_dma_multiple_
transaction_size
SD/MMC Controller
Send Feedback
29 28 27 26
13 12 11 10
Name
Burst size of multiple transaction; should be
programmed same as DMA controller multiple-
transaction-size SRC/DEST_MSIZE. The units for
transfers is 32 bits. A single transfer would be
signalled based on this value. Value should be sub-
multiple of 512. Allowed combinations for MSize and
TX_WMark.
Value
0x0
0x1
0x2
0x3
0x5
0x6
0x7
Bit Fields
25 24 23 22
rx_wmark
RW 0x3FF
9 8 7 6
tx_wmark
RW 0x0
Description
Description
Msize 1 and TX_WMARK 1-1023
Msize 4 and TX_WMARK 256
Msize 8 and TX_WMARK 128
Msize 16 and TX_WMARK 64
Msize 1 and RX_WMARK 512
Msize 4 and RX_WMARK 128
Msize 8 and RX_WMARK 64
fifoth
21 20 19 18
5 4 3 2
Access
RW
14-121
17 16
1 0
Reset
0x0
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