Altera cyclone V Technical Reference page 1133

15-44
uppwrprot
Module Instance
qspiregs
Offset:
0x50
Access:
RW
31 30
15 14
lowwrprot Fields
Bit
31:0
subsector
uppwrprot
Module Instance
qspiregs
Offset:
0x54
Access:
RW
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
The block number that defines the lower block in the
range of blocks that is to be locked from writing. The
definition of a block in terms of number of bytes is
programmable via the Device Size Configuration
register.
29 28 27 26
13 12 11 10
Base Address
0xFF705000
Bit Fields
25 24 23 22
subsector
RW 0x0
9 8 7 6
subsector
RW 0x0
Description
Base Address
0xFF705000
Bit Fields
25 24 23 22
subsector
RW 0x0
9 8 7 6
subsector
RW 0x0
Register Address
0xFF705050
21 20 19 18
5 4 3 2
Access
Register Address
0xFF705054
21 20 19 18
5 4 3 2
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
17 16
1 0
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