Altera cyclone V Technical Reference page 1039

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
clkena Fields
Bit
16
cclk_low_power
0
cclk_enable
tmout
Sets timeout values
Module Instance
sdmmc
Offset:
0x14
Access:
RW
31
30
15
14
SD/MMC Controller
Send Feedback
Name
In low-power mode, stop sdmmc_cclk_out when card
in IDLE (should be normally set to only MMC and
SD memory cards; for SDIO cards, if interrupts must
be detected, clock should not be stopped).
Value
0x0
0x1
Enables sdmmc_cclk_out.
Value
0x0
0x1
0xFF704000
29
28
27
26
13
12
11
10
data_timeout
RW 0xFFFFFF
Description
Description
Non-low-power mode
Low-power mode
Description
SD/MMC Disable
SD/MMC Enable
Base Address
Bit Fields
25
24
23
22
data_timeout
RW 0xFFFFFF
9
8
7
6
tmout
Access
Register Address
0xFF704014
21
20
19
18
5
4
3
2
response_timeout
RW 0x40
14-93
Reset
RW
0x0
RW
0x0
17
16
1
0
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents