Altera cyclone V Technical Reference page 1061

cv_5v4
2016.10.28
Bit
14
acd
13
sbe
12
hle
11
frun
10
hto
SD/MMC Controller
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Name
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Description
Description
Auto command done (ACD)
Clear Auto command done (ACD
Description
Start-bit error (SBE)
Clears Start-bit error (SBE)
Description
Hardware locked write error (HLE)
Clears Hardware locked write error (HLE)
Description
FIFO underrun/overrun error (FRUN)
Clear FIFO underrun/overrun error (FRUN)
Description
Data starvation-by-host timeout (HTO) /
Volt_switch_int
Clears Data starvation-by-host timeout
(HTO) /Volt_switch_int
14-115
rintsts
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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