Altera cyclone V Technical Reference page 1048

14-102
cmd
cmd Fields
Bit
31
start_cmd
29
use_hold_reg
28
volt_switch
27
boot_mode
Altera Corporation
Name
Once command is taken by CIU, bit is cleared. If Start
Cmd issued host should not attempt to write to any
command registers. If write is attempted, hardware
lock error is set in raw interrupt register. Once
command is sent and response is received from SD_
MMC_CEATA cards, Command Done bit is set in
raw interrupt register.
Value
0x0
0x1
Set to one for SDR12 and SDR25 (with non-zero
phase-shifted cclk_in_drv); zero phase shift is not
allowed in these modes. -Set to 1'b0 for SDR50,
SDR104, and DDR50 (with zero phase-shifted cclk_
in_drv). -Set to 1'b1 for SDR50, SDR104, and DDR50
(with non-zero phase-shifted cclk_in_drv).
Value
0x0
0x1
Voltage switch bit. When set must be set for CMD11
only.
Value
0x0
0x1
Type of Boot Mode.
Value
0x0
0x1
Description
Description
No Start Cmd
Start Cmd Issued
Description
CMD and DATA sent to card bypassing
HOLD Register
CMD and DATA sent to card through the
HOLD Register
Description
No voltage switching - default
Voltage switching enabled
Description
Mandatory Boot Operation
Alternate Boot Operation
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x1
RW 0x0
RW 0x0
SD/MMC Controller
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