Altera cyclone V Technical Reference page 1081

cv_5v4
2016.10.28
Offset:
0x8C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
fsm
RO 0x0
idsts Fields
Bit
16:13
fsm
12:10
eb
SD/MMC Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
eb
RO 0x0
Name
DMAC FSM present state.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Indicates the type of error that caused a Bus Error.
Valid only with Fatal Bus Error bit (IDSTS[2]) set.
This field does not generate an interrupt.
Value
0x1
0x2
Bit Fields
25 24 23 22
Reserved
9 8 7 6
ais nis Reserved
RW RW
0x0 0x0
Description
Description
DMA IDLE
DMA SUSPEND
DESC_RD
DESC_CHK
DMA RD REQ WAIT
DMA WR REQ WAIT
DMA RD
DMA WR
DESC CLOSE
Description
Host Abort during transmission Status Bit
Host Abort received during reception Status
Bit
21 20 19 18
5 4 3 2
ces du Reser fbe
ved
RW RW RW
0x0 0x0 0x0
Access
14-135
idsts
17 16
fsm
RO 0x0
1 0
ri ti
RW RW 0x0
0x0
Reset
RO 0x0
RO 0x0
Altera Corporation