Altera cyclone V Technical Reference page 1068

14-122
cdetect
Bit
27:16
rx_wmark
11:0
tx_wmark
cdetect
Determines if card is present.
Altera Corporation
Name
FIFO threshold watermark level when receiving data
to card. When FIFO data count reaches greater than
this number, DMA/FIFO request is raised. During
end of packet, request is generated regardless of
threshold programming in order to complete any
remaining data. In non-DMA mode, when receiver
FIFO threshold (RXDR) interrupt is enabled, then
interrupt is generated instead of DMA request.
During end of packet, interrupt is not generated if
threshold programming is larger than any remaining
data. It is responsibility of host to read remaining
bytes on seeing Data Transfer Done interrupt. In
DMA mode, at end of packet, even if remaining bytes
are less than threshold, DMA request does single
transfers to flush out any remaining bytes before Data
Transfer Done interrupt is set. 12 bits - 1 bit less than
FIFO-count of status register, which is 13 bits.
Limitation: RX_WMark <= 1022 Recommended: 511;
means greater than (FIFO_DEPTH/2) - 1) NOTE: In
DMA mode during CCS time-out, the DMA does not
generate the request at the end of packet, even if
remaining bytes are less than threshold. In this case,
there will be some data left in the FIFO. It is the
responsibility of the application to reset the FIFO
after the CCS timeout.
FIFO threshold watermark level when transmitting
data to card. When FIFO data count is less than or
equal to this number, DMA/FIFO request is raised. If
Interrupt is enabled, then interrupt occurs. During
end of packet, request or interrupt is generated,
regardless of threshold programming. In non-DMA
mode, when transmit FIFO threshold (TXDR)
interrupt is enabled, then interrupt is generated
instead of DMA request. During end of packet, on last
interrupt, host is responsible for filling FIFO with
only required remaining bytes (not before FIFO is full
or after CIU completes data transfers, because FIFO
may not be empty). In DMA mode, at end of packet,
if last transfer is less than burst size, DMA controller
does single cycles until required bytes are transferred.
12 bits - 1 bit less than FIFO-count of status register,
which is 13 bits. Limitation: TX_WMark >= 1;
Recommended: FIFO_DEPTH/2 = 512; (means less
than or equal to 512)
Description
cv_5v4
2016.10.28
Access Reset
RW 0x3FF
RW 0x0
SD/MMC Controller
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