Altera cyclone V Technical Reference page 1121

15-32
devsz
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
rddatacap Fields
Bit
4:1
delay
devsz
Module Instance
qspiregs
Offset:
0x14
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Delay the read data capturing logic by the
programmed number of qspi_clk cycles
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
bytesperdevicepage
RW 0x100
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF705000
Bit Fields
25 24 23 22
9 8 7 6
21 20 19 18
5 4 3 2
delay
RW 0x0
Access
Register Address
0xFF705014
21 20 19 18
bytespersubsector
RW 0x10
5 4 3 2
numaddrbytes
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reserved
Reset
RW 0x0
17 16
1 0
RW 0x2
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