Altera cyclone V Technical Reference page 1117

15-28
devrd
Bit
17:16
datawidth
13:12
addrwidth
Altera Corporation
Name
Sets read data transfer width (1, 2, or 4 bits).
Value
0x0
0x1
0x2
Sets read address transfer width (1, 2, or 4 bits).
Value
0x0
0x1
0x2
Description
Description
Read data transferred on DQ0. Supported by
all SPI flash devices
Read data transferred on DQ0 and DQ1.
Supported by some SPI flash devices that
support the Extended SPI Protocol and by all
SPI flash devices that support the Dual SP
(DIO-SPI) Protocol.
Read data transferred on DQ0, DQ1, DQ2,
and DQ3. Supported by some SPI flash
devices that support the Extended SPI
Protocol and by all SPI flash devices that
support the Quad SP (QIO-SPI) Protocol.
Description
Read address transferred on DQ0. Supported
by all SPI flash devices
Read address transferred on DQ0 and DQ1.
Supported by some SPI flash devices that
support the Extended SPI Protocol and by all
SPI flash devices that support the Dual SP
(DIO-SPI) Protocol.
Read address transferred on DQ0, DQ1,
DQ2, and DQ3. Supported by some SPI flash
devices that support the Extended SPI
Protocol and by all SPI flash devices that
support the Quad SP (QIO-SPI) Protocol.
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
Quad SPI Flash Controller
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