Altera cyclone V Technical Reference page 1137

15-48
indrdwater
Bit
2
rd_status
1
cancel
0
start
indrdwater
Module Instance
qspiregs
Offset:
0x64
Access:
RW
31 30
15 14
Altera Corporation
Name
Indirect read operation in progress (status)
Value
0x1
0x0
This bit will cancel all ongoing indirect read
operations.
Value
0x1
0x0
When this bit is enabled, it will trigger an indirect
read operation. The assumption is that the indirect
start address and the indirect number of bytes register
is setup before triggering the indirect read operation.
Value
0x1
0x0
29 28 27 26
13 12 11 10
Description
Description
Read Operation in progress
No read operation in progress
Description
Cancel Indirect Read
Do Not Cancel Indirect Read
Description
Trigger Indirect Read
No Indirect Read
Base Address
0xFF705000
Bit Fields
25 24 23 22
level
RW 0x0
9 8 7 6
level
RW 0x0
Access
Register Address
0xFF705064
21 20 19 18
5 4 3 2
Quad SPI Flash Controller
cv_5v4
2016.10.28
Reset
RO 0x0
RW 0x0
RW 0x0
17 16
1 0
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