Mixed-Width Support - Altera Cyclone IV Device Handbook

3–6
Figure 3–3
write cycles, respectively.
Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
Figure 3–4. Cyclone IV Devices Address Clock Enable During Write Cycle Waveform

Mixed-Width Support

M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to
page
Cyclone IV Device Handbook,
Volume 1
and Figure 3–4 show the address clock enable waveform during read and
inclock
rdaddress
a0
rden
addressstall
an a0
q (synch) doutn-1 doutn
dout0
q (asynch) doutn
inclock
a0
wraddress
data 00
wren
addressstall
latched address
an a0
(inside memory)
contents at a0 XX
contents at a1 XX
contents at a2
contents at a3
contents at a4
contents at a5
3–7.
Chapter 3: Memory Blocks in Cyclone IV Devices
a1 a2 a3
a1
dout0 dout1
dout1 dout1
a1 a2 a3
01 02
03
a1
00
01 02
XX
XX
XX
XX
Overview
a4 a5
a5
a4
dout1 dout1 dout4
dout1 dout4
dout5
a4 a5
a6
05 06
04
a4 a5
03
04
05
"Memory Modes" on
November 2011 Altera Corporation
a6