Altera cyclone V Technical Reference page 1118

cv_5v4
2016.10.28
Bit
9:8
instwidth
7:0
rdopcode
devwr
Module Instance
qspiregs
Offset:
0x8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
Quad SPI Flash Controller
Send Feedback
Name
Sets instruction transfer width (1, 2, or 4 bits). Applies
to all instructions sent to SPI flash device (not just
read instructions).
Value
0x0
0x1
0x2
Read Opcode to use when not in XIP mode
Value
0x3
0xb
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
dummywrclks
RW 0x0
13 12 11 10
addrwidth Reserved
RW 0x0
Description
Description
Instruction transferred on DQ0. Supported
by all SPI flash devices.
Instruction transferred on DQ0 and DQ1.
Supported by all SPI flash devices that
support the Dual SP (DIO-SPI) Protocol.
Instruction transferred on DQ0, DQ1, DQ2,
and DQ3. Supported by all SPI flash devices
that support the Quad SP (QIO-SPI)
Protocol.
Description
Read Opcode in Non-XIP mode
Fast Read in Non-XIP mode
Base Address
0xFF705000
Bit Fields
25 24 23 22
9 8 7 6
devwr
Access
Register Address
0xFF705008
21 20 19 18
Reserved
5 4 3 2
wropcode
RW 0x2
15-29
Reset
RW 0x0
RW 0x3
17 16
datawidth
RW 0x0
1 0
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