Altera cyclone V Technical Reference page 1012

14-66
Register Settings for ATA Payload Transfer
Bits
ccs_expected
read_ceata_device
update_clk_regs_only
card_num
send_initialization
stop_abort_cmd
send_auto_stop
transfer_mode
read_write
data_expected
response_length
response_expect
cmd_index
wait_prvdata_complete
check_response_crc
Table 14-34: blksiz Register Settings for ATA Payload Transfer
Bits
31:16
Altera Corporation
Value
1 CCS is expected. Set to 1 for the RW_BLK
command if interrupts are enabled in CE-ATA
card device (the
control register)
0 or 1 Set to 1 for a RW_BLK or RW_REG read
command
0 No clock parameters update command
0
0 No initialization sequence
0
0
0 Block transfer mode. Byte count must be integer
multiple of 4kB. Block size can be 512, 1k or 4k
bytes
1 or 0 1 for write and 0 for read
1 Data is expected
0
1
Command index Set this parameter to the command number. For
example, set to 24 for SD/SDIO WRITE_BLOCK
(CMD24) or 25 for WRITE_MULTIPLE_BLOCK
(CMD25).
1 • 0 for send command immediately
• 1 for send command after previous DTO
1 • 0 for not checking response CRC
• 1 for checking response CRC
Value
0
Comment
bit is set to 0 in the ATA
nIEN
-
-
-
-
-
interrupt
†
Reserved bits set to 0
cv_5v4
2016.10.28
Comment
SD/MMC Controller
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