Altera cyclone V Technical Reference page 1074

14-128
hcon
31 30
Reserved
15 14
haddrwidth
hcon Fields
Bit
26
aro
25:24
ncd
23
scfp
22
ihr
21
rios
Altera Corporation
29 28 27 26
aro
RO
0x0
13 12 11 10
RO 0xC
Name
Area optimized
Value
0x0
Number of clock dividers less one
0x0
Clock False Path
0x1
Implement hold register
Value
0x1
FIFO RAM location
Value
0x0
Bit Fields
25 24 23 22
ncd scfp ihr
RO 0x0 RO RO
0x1 0x1
9 8 7
hdatawidth hbus
RO 0x1 RO
0x0
Description
Description
Not Optimized For Area
Value
One Clock Divider
Value Description
Clock False Path Set
Description
Implements Hold Register
Description
FIFO RAM Outside IP Core
21 20 19
rios dmadatawidth
RO RO 0x1
0x0
6 5 4 3
nc
RO 0x0
Description
cv_5v4
2016.10.28
18 17 16
dmaintf
RO 0x0
2 1 0
ct
RO 0x1
Access Reset
RO 0x0
RO 0x0
RO 0x1
RO 0x1
RO 0x0
SD/MMC Controller
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