Altera cyclone V Technical Reference page 1056

14-110
mintsts
Offset:
0x3C
Access:
RO
31 30
15 14
resp3 Fields
Bit
31:0
response3
mintsts
Describes state of Masked Interrupt Register.
Module Instance
sdmmc
Offset:
0x40
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ebe acd strer
RO 0x0 RO
0x0
Altera Corporation
29 28 27 26
13 12 11 10
Name
Bit[127:96] of long response
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
hlwer fifoo dshto
r r vuner
RO
r
RO RO 0x0
0x0 0x0 RO
0x0
Bit Fields
25 24 23 22
response3
RO 0x0
9 8 7 6
response3
RO 0x0
Description
Base Address
0xFF704000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
datar respt datac respc
dto o rcerr rcerr
RO RO RO RO
0x0 0x0 0x0 0x0
21 20 19 18
5 4 3 2
Register Address
0xFF704040
21 20 19 18
5 4 3 2
rxfif dttxf dt cmd_
odr ifodr done
RO
RO RO 0x0 RO
0x0 0x0 0x0
cv_5v4
2016.10.28
17 16
1 0
Access Reset
RO 0x0
17 16
sdio_
interrup
t
RO 0x0
1 0
resp cd
RO RO 0x0
0x0
SD/MMC Controller
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