Altera cyclone V Technical Reference page 1035

cv_5v4
2016.10.28
Bit
6
read_wait
4
int_enable
2
dma_reset
1
fifo_reset
0
controller_reset
pwren
Power on/​off switch for card; once power is turned on, firmware should wait for regulator/switch ramp-up
time before trying to initialize card.
SD/MMC Controller
Send Feedback
Name
For sending read-wait to SDIO cards.
Value
0x0
0x1
This bit enables and disable interrupts if one or more
unmasked interrupts are set.
Value
0x0
0x1
This bit resets the DMA interface control logic
Value
0x0
0x1
This bit resets the FIFO. This bit is auto-cleared after
completion of reset operation.
Value
0x0
0x1
This bit resets the controller. This bit is auto-cleared
after two l4_mp_clk and two sdmmc_clk clock cycles.
This resets: - BIU/CIU interface - CIU and state
machines - abort_read_data, send_irq_response, and
read_wait bits of control register -start_cmd bit of
command register Does not affect any registers, DMA
interface, FIFO or host interrupts.
Value
0x0
0x1
Description
Description
Read Wait
Assert Read Wait
Description
Disable Interrupts
Enable interrupts
Description
No change
Reset internal DMA interface control logic
Description
No change
Reset to data FIFO To reset FIFO pointers
Description
No change -default
Reset SD/MMC controller
14-89
pwren
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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