Altera cyclone V Technical Reference page 1138

cv_5v4
2016.10.28
indrdwater Fields
Bit
31:0
level
indrdstaddr
Module Instance
qspiregs
Offset:
0x68
Access:
RW
31 30
15 14
indrdstaddr Fields
Bit
31:0
addr
indrdcnt
Module Instance
qspiregs
Quad SPI Flash Controller
Send Feedback
Name
This represents the minimum fill level of the SRAM
before a DMA peripheral access is permitted. When
the SRAM fill level passes the watermark, an interrupt
is also generated. This field can be disabled by writing
a value of all zeroes. The units of this register are
BYTES
0xFF705000
29 28 27 26
13 12 11 10
Name
This is the start address from which the indirect
access will commence its READ operation.
0xFF705000
Description
Base Address
Bit Fields
25 24 23 22
addr
RW 0x0
9 8 7 6
addr
RW 0x0
Description
Base Address
indrdstaddr
Access
Register Address
0xFF705068
21 20 19 18
5 4 3 2
Access
Register Address
0xFF70506C
15-49
Reset
RW 0x0
17 16
1 0
Reset
RW 0x0
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