Altera cyclone V Technical Reference page 1009

cv_5v4
2016.10.28
1. Write the data size in bytes to the
controller expects a single block transfer.
2. Write the block size in bytes to the
3. Write the
You must set the
ATA Task File Transfer.
Related Information
Register Settings for ATA Task File Transfer
Refer to this table for information on how to set these registers.
Register Settings for ATA Task File Transfer
Table 14-28: cmdarg Register Settings for ATA Task File Transfer
Bit
31
30:24
23:18
17:16
15:8
7:2
1:0
Table 14-29: cmd Register Settings for ATA Task File Transfer
Bit
start_cmd
ccs_expected
read_ceata_device
update_clk_regs_only
card_num
send_initialization
stop_abort_cmd
SD/MMC Controller
Send Feedback
bytcnt
register with the beginning register address.
cmdarg
, , , and
cmdarg cmd blksiz
†
Value
1 or 0 Set to 0 for read operation or set to 1 for write operation
0 Reserved (bits set to 0 by host processor)
0 Starting register address for read or write (DWORD aligned)
0 Register address (DWORD aligned)
0 Reserved (bits set to 0 by host processor)
16 Number of bytes to read or write (integral number of DWORD)
0 Byte count in integral number of DWORD
Value
1
0
0 or 1
0
0
0
0
Register Settings for ATA Task File Transfer
register. must equal the block size, because the
bytcnt
†
†
register.
blksiz
registers according to the tables in Register Settings for
bytcnt
on page 14-63
†
†
CCS is not expected
Set to 1 if RW_BLK or RW_REG read
No clock parameters update command
No initialization sequence
†
Comment
Comment
14-63
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