Altera cyclone V Technical Reference page 1131

15-42
irqmask
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
irqmask Fields
Bit
12
indsramfull
11
rxfull
10
rxthreshcmp
9
txfull
8
txthreshcmp
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
indsr rxful rxthr
amful l eshcm
l p
RW
RW 0x0 RW
0x0 0x0
Name
Value
0x0
0x1
Value
0x0
0x1
Value
0x0
0x1
Value
0x0
0x1
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
txful txthr rxove indxf
l eshcm r rlvl
p
RW RW RW
0x0 RW 0x0 0x0
0x0
Description
Description
Disable Interrupt by Masking
Enable Interrupt
Description
Disable Interrupt by Masking
Enable Interrupt
Description
Disable Interrupt by Masking
Enable Interrupt
Description
Disable Interrupt by Masking
Enable Interrupt
Description
Disable Interrupt by Masking
Enable Interrupt
21 20 19 18
5 4 3 2
illeg protw indrd indop
alacc ratte rejec done
mpt t
RW RW
0x0 RW RW 0x0
0x0 0x0
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
under Reserved
flowd
et
RW
0x0
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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