Enabling And Initially Starting A Watchdog Timer - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Enabling and Initially Starting a Watchdog Timer

To enable and start a watchdog timer, write the value 1 to the watchdog timer enable bit (
register.
wdt_cr
Reloading a Watchdog Counter
To reload a watchdog counter, write the value 0x76 to the counter restart register (
8-bit value is used as a safety feature to prevent accidental restarts.
Pausing a Watchdog Timer
Pausing the watchdog timers is controlled by the L4 watchdog debug register (
manager.
Related Information
Features of the System Manager
For more information, refer to the System Manager chapter.
Disabling and Stopping a Watchdog Timer
The watchdog timers are disabled and stopped by resetting them from the reset manager.
Related Information
Reset Manager
For more information, refer to the Reset Manager chapter.
Watchdog Timer State Machine
The following figure illustrates the behavior of the watchdog timer, including the behavior of both output
response modes. Once initialized, the counter decrements at every clock cycle. The state machine remains
in the Decrement Counter state until the counter reaches zero, or the watchdog timer is restarted. If
software reads the interrupt clear register (
changes from Decrement Counter to Load Counter with Restart Timeout Value. In this state, the
watchdog counter gets reloaded with the restart timeout value, and then the state changes back to
Decrement Counter.
Watchdog Timer
Send Feedback
on page 5-1
on page 3-1
Enabling and Initially Starting a Watchdog Timer
), or writes 0x76 to the
wdt_eoi
) of the
wdt_en
). This unique
wdt_crr
) in the system
wddbg
register, the state
wdt_crr
Altera Corporation
24-5