Servicing Interrupts - Altera cyclone V Technical Reference

23-6

Servicing Interrupts

Servicing Interrupts
Clearing the Interrupt
An active timer interrupt can be cleared in two ways.
1. If you clear the interrupt at the same time as the timer reaches 0, the interrupt remains asserted. This
action happens because setting the timer interrupt takes precedence over clearing the interrupt. †
2. To clear an active timer interrupt, read the
enabled, its interrupt remains asserted until it is cleared by reading the
Checking the Interrupt Status
You can query the interrupt status of the timer without clearing its interrupt.
1. To check the interrupt status, read the
Masking the Interrupt
The timer interrupt can be masked using the
To mask an interrupt, write a 1 to the
Timer Address Map and Register Definitions
The address map and register definitions for the HPS-FPGA bridges consist of the following regions:
• OSC1 Timer Module 0
• OSC1 Timer Module 1
• SP Timer Module 0
• SP Timer Module 1
Related Information
Introduction to the Hard Processor System
•
For more information, refer to the Introduction to the Hard Processor System chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
Timer Module Address Map
Registers in the timer module. The timer IP core supports multiple timers but it is configured for just one
timer. The term Timer1 refers to this one timer in the IP core and not the module instance.
sptimer0
sptimer1
osc1timer0
osc1timer1
Altera Corporation
Module Instance
register or disable the timer. When the timer is
timer1eoi
register. †
timer1intstat
timer1controlreg
timer1_interrupt_mask
on page 1-1
0xFFC08000
0xFFC09000
0xFFD00000
0xFFD01000
register. †
timer1eoi
register.
bit of the
timer1controlreg
Base Address
cv_5v4
2016.10.28
register. †
Timer
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