Watchdog Timer Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Watchdog Timer Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridge consist of the following regions:
• L4 Watchdog Module 0
• L4 Watchdog Module 1
Related Information
• Introduction to the Hard Processor System
For more information, refer to the Introduction to the Hard Processor System chapter.
• http://www.altera.com/literature/hb/cyclone-v/hps.html
L4 Watchdog Module Address Map
Registers in the L4 Watchdog module
l4wd0
l4wd1
L4 Watchdog Module
Register
wdt_cr on page 24-8
wdt_torr on page 24-
9
wdt_ccvr on page 24-
11
wdt_crr on page 24-
12
wdt_stat on page 24-
13
wdt_eoi on page 24-
14
cp_wdt_user_top_max
on page 24-14
cp_wdt_user_top_init_
max on page 24-15
cd_wdt_top_rst
page 24-16
cp_wdt_cnt_rst
page 24-16
Watchdog Timer
Send Feedback
Module Instance
Offset Width Acces
0x0
0x4
0x8
0xC
0x10
0x14
0xE4
0xE8
on 0xEC
on 0xF0
Watchdog Timer Address Map and Register Definitions
on page 1-1
0xFFD02000
0xFFD03000
Reset Value
s
32 RW 0x2
32 RW 0xFF
32 RO 0x7FFFFFFF
32 WO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0xFF
32 RO 0x7FFFFFFF
Base Address
Description
Control Register
Timeout Range Register
Current Counter Value Register
Counter Restart Register
Interrupt Status Register.
Interrupt Clear Register
Component Parameters Register 5
Component Parameters Register 4
Component Parameters Register 3
Component Parameters Register 2
Altera Corporation
24-7