Timer Programming Model - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Timer Programming Model

Initialization
To initialize the timer, perform the following steps: †
1. Initialize the timer through the
• Disable the timer by writing a 0 to the timer1 enable bit (
timer1controlreg
Note: Before writing to a timer1 load count register (
by writing a 0 to the
synchronization problems. †
• Program the timer mode—user-defined count or free-running—by writing a 0 or 1, respectively, to
the timer1 mode bit (
• Set the interrupt mask as either masked or not masked by writing a 1 or 0, respectively, to the
timer1_interrupt_mask
2. Load the timer counter value into the
3. Enable the timer by writing a 1 to the
Enabling the Timer
When a timer transitions to the enabled state, the current value of
into the timer counter. †
1. To enable the timer, write a 1 to the
Disabling the Timer
When the timer enable bit is cleared to 0, the timer counter and any associated registers in the timer clock
domain, are asynchronously reset. †
1. To disable the timer, write a 0 to the
Loading the Timer Countdown Value
When a timer counter is enabled after being reset or disabled, the count value is loaded from the
timer1loadcount
When a timer counts down to 0, it loads one of two values, depending on the timer operating mode: †
• User-defined count mode—timer loads the current value of the
mode if you want a fixed, timed interrupt. Designate this mode by writing a 1 to the
of the
timer1controlreg
• Free-running mode—timer loads the maximum value (0xFFFFFFFF). The timer max count value
allows for a maximum amount of time to reprogram or disable the timer before another interrupt
occurs. Use this mode if you want a single timed interrupt. Enable this mode by writing a 0 to the
timer1_mode
Timer
Send Feedback
timer1controlreg
register. †
timer1_enable
) of the
timer1_mode
bit of the
timer1loadcount
timer1_enable
timer1_enable
timer1_enable
register; this occurs in both free-running and user-defined count modes. †
register. †
bit of the
timer1controlreg
register: †
timer1_enable
timer1loadcount
bit of the
timer1controlreg
timer1controlreg
register. †
timer1controlreg
register. †
bit of the
timer1controlreg
timer1loadcount
bit of the
timer1controlreg
bit. †
timer1loadcount
register. †
Timer Programming Model
) of the
), you must disable the timer
register to avoid potential
register. †
register. †
register is loaded
register.
register. Use this
timer1_mode
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