Watchdog Timer Block Diagram And System Integration - Altera cyclone V Technical Reference

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Watchdog Timer Block Diagram and System Integration

Watchdog Timer Block Diagram and System Integration
Each watchdog timer consists of a slave interface for control and status register (CSR) access, a register
block, and a 32-bit down counter that operates on the slave interface clock (
driven by the system manager, optionally pauses the counter when a CPU is being debugged.
The watchdog timer drives an interrupt request to the MPU and a reset request to the reset manager.
Figure 24-1: Watchdog Timer Block Diagram
Related Information
Reset Manager
•
For more information, refer to the Reset Manager chapter.
Cortex-A9 Microprocessor Unit Subsystem
•
For more information about the watchdog timers in the MPU, refer to Cortex A9 Microprocessor Unit
Subsystem chapter.
Functional Description of the Watchdog Timer
Watchdog Timer Counter
Each watchdog timer is a programmable, little-endian down counter that decrements by one on each clock
cycle. The watchdog timer supports 16 fixed timeout period values, Software chooses which timeout
periods are desired. A timeout period is 2<n>
inclusive.
Software must regularly restart the timer (which reloads the counter with the restart timeout period value)
to indicate that the system is functioning normally. Software can reload the counter at any time by writing
to the restart register. If the counter reaches zero, the watchdog timer has timed out, indicating an
unrecoverable error has occurred and a system reset is needed.
Altera Corporation
Watchdog Timer
System
Pause
Manager
L4 Peripheral Bus (osc1_clk)
on page 3-1
Reset
Request
Interrupt &
System Reset
Interrupt
Control
Register Block
Slave Interface
on page 9-1
clock periods, where n is an integer from 16 to 31
osc1_clk
). A pause input,
osc1_clk
Reset
Manager
MPU
Watchdog Timer
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cv_5v4
2016.10.28