Altera cyclone V Technical Reference page 1170

cv_5v4
2016.10.28
DMALPEND
# Perform final transaction (16 of 16). Send the peripheral acknowledgement
of burst request completion
DMALD
DMASTPB 0
# Finish burst loop
DMALPEND
# Set up for AXI single transfer (word data width, so SS32 and DS32)
DMAMOV CCR SB1 SS32 DB1 DS32
# Single request loop to transfer 3 words
DMALP 3
# Wait for the peripheral to signal a single request. DMAC to transfer one
word
DMAWFP 0, single
# Perform transaction for single request and send completion acknowledgement
to the peripheral
DMALDS
DMASTPS P0
# Finish single loop
DMALPEND
# Flush the peripheral, in case the single transfers were in response to a
burst request
DMAFLUSHP 0
DMAEND
Peripheral Request Interface Timing Diagrams
The following are examples of the functional operation of the peripheral request interface using the rules
that the "Handshake Rules" chapter describes.
Related Information
Handshake Rules
Burst Request
DMA request timing when a peripheral requests a burst transfer.
Figure 16-4: Burst Request Signaling
DMA Controller
Send Feedback
on page 16-11
Peripheral Request Interface Timing Diagrams
16-19
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