Altera cyclone V Technical Reference page 1153

16-2
Features of the DMA Controller
The DMAC supports the following interface protocols:
• Synopsys protocol
• Serial peripheral interface (SPI)
• Universal asynchronous receiver/transmitter (UART)
• Inter-integrated circuit (I
• FPGA
• ARM protocol
• Quad SPI flash controller
• System trace macrocell (STM)
• Bosch CAN
• Two CAN controllers
Dual slave interfaces enable the operation of the DMA controller to be partitioned into the secure state
and non-secure state. The network interconnect must be configured to ensure that only secure transac‐
tions can access the secure interface. The slave interfaces can access status registers and also directly
execute instructions in the DMA controller.
The DMAC has the following features:
• A small instruction set that provides a flexible method of specifying the DMA operations. This
architecture provides greater flexibility than the fixed capabilities of a Linked-List Item (LLI) based
DMA controller.
• Supports multiple transfer types:
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
• Scatter-gather
• Supports up to eight DMA channels.
• Supports up to eight outstanding AXI read and eight outstanding AXI write transactions.
• Enables software to schedule up to 16 outstanding read and (16) outstanding write instructions.
• Supports 11 interrupt lines into the MPU subsystem
• One for DMA thread abort
• Eight for events
• Two for MFIFO buffer ECC
• Single and double bit ECC support
• Supports 31 peripheral request interfaces:
• Four for FPGA
• Four shared for FPGA or Controller area network (CAN)
• Four for I
• Four for I
• Eight for SPI
• Two for quad SPI
• One for System Trace Macrocell (STM)
• Four for UART
(53) For a description of these interrupts, refer to the "Using Events and Interrupts" chapter.
Altera Corporation
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cv_5v4
2016.10.28
DMA Controller
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